Abstract
This paper describes the design of a 12-bit successive approximation register (SAR) analog-to-digital converter (ADC) designed and fabricated using 0.18 mu m CMOS process. The ADC operates with a supply voltage from 0.9V to 1.4V and up to 20kS/s sampling rate. Using charge-scaling technique and a modified dynamic comparator structure, the ADC consumes only 100nW at V(dd) = 0.9V and 1kS/s sampling rate. The ADC was tested and verified for phonocardiography and heart-rate counting.