Abstract
This paper presents a low power 2.4-GHz fully integrated 1 MHz resoltuion IEEE 802.15.4 frequency sysnthesizer designed using 0.18 mu m CMOS technology. An integer-N fully programmable divider employs a novel True-single-phase-clock (TSPC) 47/48 prescaler and 6 bit P and S counters to provide the 1MHz output with nearly 45% duty cycle. The PLL uses a series quadrature voltage controlled oscillator (S-QVCO) to generate quadrature signals. The PLL consumes 3.6 mW of power at 1.8 V supply with the fully programmable divider consuming only 600 mu W. The S-QVCO consumes 2.8 mW of power with a phase noise of -122.4 dBc/Hz at 1MHz offset.