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A 18-to-22 GHz 22.8 dBm PSAT 18.2 dB Gain Power Amplifier in 0.13-μm CMOS SOI
Conference proceeding

A 18-to-22 GHz 22.8 dBm PSAT 18.2 dB Gain Power Amplifier in 0.13-μm CMOS SOI

Guiyue Mao, Fanyi Meng and IEEE
Global Symposium on Millimeter Waves (Online), pp.231-233
20/05/2024
DOI: https://doi.org/10.1109/GSMM61775.2024.10553183

Abstract

Bandwidth Capacitors Circuit faults CMOS technology K-band Network topology PAE power amplifier Power amplifiers power combiner SOI CMOS Topology
This paper presents a 18-22 GHz stacked power amplifier (PA) in 0.13-μm CMOS SOI technology. The amplifier adopts cascode unit topology, and utilizes twoway power combining networks to improve the output power. Neutralization capacitor is customized in the design to enhance the stability and in-band gain flatness. The PA achieves a small-signal gain of 18.2dB and 3-dB bandwidth (BW) of 10 GHz, a 1-dB compressed power (P1dB) of 18.2 dBm and a saturated output power (PSAT) of 22.8 dBm with a peak PAE of 29.0%. The PA chip area is 0.44 mm 2 including the pads.

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