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A 60-GHz 26.3-dB gain 5.3-dB NF low-noise amplifier in 65-nm CMOS using Q-factor enhanced inductors
Conference proceeding

A 60-GHz 26.3-dB gain 5.3-dB NF low-noise amplifier in 65-nm CMOS using Q-factor enhanced inductors

Fanyi Meng, Kaixue Ma, Kiat Seng Yeo, Shanshan Xu, Chirn Chye Boon and Wei Meng Lim
The Institute of Electrical and Electronics Engineers, Inc. (IEEE) Conference Proceedings, p.1
01/08/2014

Abstract

Conference Title: 2014 XXXIth URSI General Assembly and Scientific Symposium (URSI GASS) Conference Start Date: 2014, Aug. 16 Conference End Date: 2014, Aug. 23 Conference Location: Beijing, China In this paper, a 60-GHz high gain low-noise amplifier is designed and verified experimentally. Firstly, inductors with asymmetrical ground plane are introduced and studied by using EM simulation, obtains an improvement of quality-factor. Then, a three-stage cascade low-noise amplifier using the proposed inductors is designed. Fabricated in Global Foundries 65-nm CMOS process, the low-noise amplifier features a peak gain of 26.3 dB with 21.8 mW DC power consumption, a noise figure of 5.3 dB, an average output P1dB of -4 dBm, and a core size of 0.15 mm2. In the comparison with prior arts, the proposed design achieves the highest gain and figure-of-merit.

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