Abstract
Conference Title: 2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Conference Start Date: 2016, May 22 Conference End Date: 2016, May 24 Conference Location: San Francisco, CA, USA A fully integrated 93.4-to-104.8 GHz 57 mW cascaded PLL, with true in-phase injection-coupled QVCO, occupies 0.88 mm2 in 65 nm CMOS. By cascading the fractional-N PLL and the sub-sampling PLL, good phase noise, high resolution and wide acquisition range are achieved simultaneously. The measured phase noise of QVCO and PLL are -112.67 and -108.75 dBc/Hz at 10 MHz offset, respectively. The FOM and FOMT of the QVCO at 10 MHz offset are -177.5 and -179.0 dBc/Hz, respectively.