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A Delta-Sigma Fractional-N frequency divider for A Phase Lock Loop in 60GHz Transceiver
Conference proceeding

A Delta-Sigma Fractional-N frequency divider for A Phase Lock Loop in 60GHz Transceiver

Yisheng Wang, Kaixue Ma, Nagarajan Mahalingam, Kiat Seng Yeo and IEEE
2011 INTERNATIONAL CONFERENCE OF ELECTRON DEVICES AND SOLID-STATE CIRCUITS (EDSSC)
IEEE International Conference on Electron Devices and Solid-State Circuits
01/01/2011

Abstract

Engineering Engineering, Electrical & Electronic Physical Sciences Physics Physics, Applied Science & Technology Technology
A design and optimization flow for digital delta-sigma fractional-N frequency divider of Phase Lock Loop (PLL) is introduced in this paper. The low power design is used for the 60 GHz RF transceiver using 0.18um SiGe BiCMOS technology. With full consideration of the low complexity and unconditional stability, MASH111 delta-sigma modulator is chosen as control module for the PLL. The input frequency is 6.48Ghz, and the integer division rate is from 36 to 64 with step of 2.

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