Abstract
This brief presents a high-power-density amplifier utilizing a compact triple-coil interweaved parallel combining transformer (TIPC) and a modified low-loss three-way parallel power splitter for transformation from single-ended to triple-ended (S3D) in the 0.13-mu m CMOS SOI process. The power amplifier (PA) is based on a differential three-stack-transistor (TST) configuration, a ladder-type interconnection method and the RC feedback technique to reduce reflection loss and balance maximum available gain and stability. And the PA utilizes an improved zero-degree combiner (ZDC) with high-quality factor (Q-factor) metal-insulator-metal (MIM) capacitors and well-designed pattern ground to reduce the loss of passive matching networks. Therefore, the silicon-based PA shows a competitive power density of 1.319 W/mm(2). Simulated results demonstrate that this PA exhibits a peak gain of 18.3 dB at 7.1 GHz and a 50% bandwidth from 6 to 10 GHz. Due to the proposed three-way splitter and TIPC combiner, the PA achieves a power-added efficiency ( PAE) of 38.4%, saturation output power (P-SAT) up to 28.2 dBm within a compact size of 0.501 mm(2).