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A Low Power Low Voltage Gain Controllable Sigma-Delta Modulator
Conference proceeding

A Low Power Low Voltage Gain Controllable Sigma-Delta Modulator

Xinbo Qian, T. Hui Teo and IEEE
TENCON 2009 - 2009 IEEE REGION 10 CONFERENCE, VOLS 1-4, pp.251-254
TENCON IEEE Region 10 Conference Proceedings
01/01/2009

Abstract

Computer Science Computer Science, Interdisciplinary Applications Engineering Engineering, Electrical & Electronic Science & Technology Technology Telecommunications
A switch-capacitor SDM with a controllable gain design at the signal input stage has been proposed. This gain control is realized by increasing the input sampling capacitors to obtain a higher signal gain of the first integrator. This method can greatly reduce the switch-capacitor thermal noise due to the input sampling capacitors without degrading the SDM noise shaping feature. The adaptive gain control can be achieved by tracking the input signal strength. The design consumes 24 mu W from a 1 V supply. It was fabricated in a 0.18 mu m CMOS technology. The modulator's SNDR for a 5 mVp-p small input signal increases from 26 dB to 33 dB with a gain factor of 4, and the ENOB of the gain controlled SDM is also improved from 10 bit to 11 bit.

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