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A New Phase Noise Model for TSPC based divider
Conference proceeding

A New Phase Noise Model for TSPC based divider

X.P. Yu, M.A. Do, J.G. Ma and K.S. Yeo
2006 IFIP International Conference on Very Large Scale Integration, pp.348-351
10/2006
DOI: https://doi.org/10.1109/VLSISOC.2006.313259

Abstract

Circuit noise Energy consumption Frequency conversion Jitter Noise measurement Phase locked loops Phase measurement Phase noise Signal to noise ratio Synthesizers
A new time variant model for the time domain jitter in the TSPC frequency divider is proposed. The trade-off between the phase noise and power consumption in the prescaler design is analyzed. Based on the analysis, a new prescaler that has a better balance among the operating frequency, power consumption and phase noise is proposed. The analysis is verified by the simulation and measured results in this prescaler

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