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A new 5 GHz CMOS dual-modulus prescaler
Conference proceeding

A new 5 GHz CMOS dual-modulus prescaler

X.P. Yu, M.A. Do, J.G. Ma and K.S. Yeo
2005 IEEE International Symposium on Circuits and Systems (ISCAS), pp.5027-5030 Vol. 5
2005

Abstract

Circuits Delay Detectors Energy consumption Equations Frequency conversion Frequency synthesizers Robust control Switches Topology
A new prescaler based on an improved phase switching method is proposed. It reduces the complexity of the existing phase switching architecture, while maintaining robust control during operation. Different from the conventional way, in the new prescaler, the duty cycle of the switched signal is manually modified in advance to reduce the error window, and, as a result, the operating speed and power consumption can be well-balanced and free of glitches. The proposed divide-by 7/8 prescaler, using the Chartered 0.18 /spl mu/m CMOS process, is capable of operating up to 5 GHz for a 1.8 V supply voltage with 10 mW power consumption.

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