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A novel de-embedding technique for On-Wafer characterization of RF CMOS
Conference proceeding

A novel de-embedding technique for On-Wafer characterization of RF CMOS

X.S. Loo, K.S. Yeo, K.W.J. Chew, L.H.K. Chan, S.N. Ong, M.A. Do, C.C. Boon and IEEE
2009 International SoC Design Conference, pp.29-32
11/2009
DOI: https://doi.org/10.1109/SOCDC.2009.5423849

Abstract

Circuit testing CMOS technology De-embedding Fixture parasitic Fixtures Geometry High frequency characterization Industrial electronics Integrated circuit interconnections Radio frequency RF CMOS Scattering parameters Semiconductor device modeling Silicon
A novel de-embedding technique based on general fixture model is proposed to accurately de-embed the test fixture parasitic for characterization of RF CMOS at high frequency. The method is able to avoid over-de-embedding errors that exist in conventional techniques by utilizing three Thru structures of zero length and one Open dummy test structures for accurate extraction of fixture parasitic. The de-embedding result is verified with Thru line replaced as intrinsic device and has been shown matching closer to the actual intrinsic Thru line than other compared techniques for frequency of up to 50 GHz.

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