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An ultra low-power output feedback flip-flop
Conference proceeding

An ultra low-power output feedback flip-flop

Myint Wai Phyu, Wang Ling Goh and Kiat Seng Yeo
The 2004 IEEE Asia-Pacific Conference on Circuits and Systems : proceedings, SoC design for ubiquitous information technology, December 6-9, 2004, Tayih Landis Hotel, Tainan, Taiwan, Vol.1, pp.341-344 vol.1
2004
DOI: https://doi.org/10.1109/APCCAS.2004.1412765

Abstract

Circuit simulation Clocks Delay Digital systems Energy consumption Flip-flops Inverters Latches Output feedback Power dissipation
In this paper, we proposed a new low-power output feedback single edge-triggered flip-flop (FBFF) that eliminates unnecessary internal transitions at the precharge node. As a result, the proposed FBFF is able to achieve substantial power reduction with no impact on its latency. The comparison of simulation results had indicated a maximum power saving of 87.9% during low input activities and an enhanced power-delay-product (in terms of the clock-to-output delay) of 8%-50%

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