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Area efficient low-power static explicit-pulsed flip-flop with local feedback
Conference proceeding

Area efficient low-power static explicit-pulsed flip-flop with local feedback

K. S. Yeo, W. L. Goh, M. W. Phyu and IEEE
2005 IEEE Conference on Electron Devices and Solid-State Circuits, pp.735-738
IEEE International Conference on Electron Devices and Solid-State Circuits
01/01/2005
DOI: https://doi.org/10.1109/EDSSC.2005.1635381

Abstract

Engineering Engineering, Electrical & Electronic Instruments & Instrumentation Physical Sciences Physics Physics, Condensed Matter Science & Technology Technology
In this paper, a static explicit-pulsed single/double edge-triggered flip-flop suitable for low-power application is presented. It offers energy savings by reduction unnecessary internal switching activities. All circuits are simulated in 0.18-mu m CMOS technology with a supply voltage of 1.8V. The developed circuit provides up to 18.1% total gate-area reduction and also 19.4% improvement in the power-delay over the best performing flip-flop reported to-date.

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