Atomic Scale Strain Measurement for Nanoelectronic Devices

Chih Hang Tlung; Kin Leong Pey; Fu Qinrong; Bud Fox

doi:10.1109/IPFA.2007.4378052

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Conference proceeding

Atomic Scale Strain Measurement for Nanoelectronic Devices

Chih Hang Tlung, Kin Leong Pey, Fu Qinrong and Bud Fox

2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits, pp.30-33

07/2007

DOI: https://doi.org/10.1109/IPFA.2007.4378052

Abstract

Atomic measurements

Diffraction

Electrons

Lattices

MOSFET circuits

Nanoscale devices

Production

Silicon

Spatial resolution

Strain measurement

Atomic scale lattice strain measurement using high resolution transmission electron microscopic (HR- TEM) is an important application for semiconductor device characterization. Recent advancement and issues in these areas are discussed. Their potential applications in contemporary sub-45 nm metal-oxide- semiconductor field effect transistor (MOSFET) technology nodes are crucial. Major technical limitation in using these characterization techniques in wafer production environment is discussed and solution proposed.

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Title: Atomic Scale Strain Measurement for Nanoelectronic Devices
Creators - without role: Chih Hang Tlung - Institute of Microelectronics
Kin Leong Pey - Nanyang Technological University
Fu Qinrong - Institute of High Performance Computing
Bud Fox - Institute of High Performance Computing
Publication Details: 2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits, pp.30-33
Publisher: IEEE
Number of pages: 4
Identifiers: 9914227409846
Academic Unit: Engineering Product Development (EPD); Temasek Lab
Language: English
Resource Type: Conference proceeding

Atomic Scale Strain Measurement for Nanoelectronic Devices

Abstract

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