Characterization of on-wafer vias for CMOS RFICs

Xiaomeng Shi; Kiat Seng Yeo; Manh Anh Do; Chirn Chye Boon; IEEE

doi:10.1109/ISICIR.2007.4441830

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Characterization of on-wafer vias for CMOS RFICs

Xiaomeng Shi, Kiat Seng Yeo, Manh Anh Do, Chirn Chye Boon and IEEE

2007 International Symposium on Integrated Circuits, pp.192-195

01/01/2007

DOI: https://doi.org/10.1109/ISICIR.2007.4441830

Abstract

Engineering

Engineering, Electrical & Electronic

Science & Technology

Technology

Characterization of a single on-wafer via using a 0.18-mu m RFCMOS technology is presented in this paper. The equivalent resistance and inductance of the via are extracted from full wave simulations up to 30 GHz frequency range. The de-embedding method is also discussed.

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Title: Characterization of on-wafer vias for CMOS RFICs
Creators - without role: Xiaomeng Shi - Nanyang Technological University
Kiat Seng Yeo - Nanyang Technological University
Manh Anh Do - Supreme Council Of Health
Chirn Chye Boon - Nanyang Technological University
IEEE
Publication Details: 2007 International Symposium on Integrated Circuits, pp.192-195
Publisher: IEEE
Number of pages: 4
Identifiers: 9911714709846
Academic Unit: Office of Provost
Language: English
Resource Type: Conference proceeding

Characterization of on-wafer vias for CMOS RFICs

Abstract

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