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Design and implementation of multiple addresses parallel transmission architecture for storage area network
Conference proceeding

Design and implementation of multiple addresses parallel transmission architecture for storage area network

Bin Meng, P.B.T. Khoo and T.C. Chong
20th IEEE/11th NASA Goddard Conference on Mass Storage Systems and Technologies (MSST 2003) : proceedings : San Diego, California, 7-10 April 2003, pp.67-71
2003
DOI: https://doi.org/10.1109/MASS.2003.1194838

Abstract

Availability Bandwidth Fault tolerance Hardware Load management Network topology Packet switching Protocols Scheduling Storage area networks
In this paper we present a parallel transmission architecture for the storage area network (SAN). By using two schedulers on the destination and source addresses of packets, the load of multiple data flows between multiple devices can be balanced in an asymmetrical topology without using special hardware. The SAN performance could be scaled flexibly and an additional fault tolerance feature is provided. The load balancing algorithms we provide can be easily implemented and the computation is efficient enough for high-speed transmission.

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