High Energy Efficient Ultra-low Voltage SRAM Design: Device, Circuit, and Architecture

Tony T. Kim; Bo Wang; Anh Tuan Do; IEEE

doi:10.1109/ISOCC.2012.6407117

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Conference proceeding

High Energy Efficient Ultra-low Voltage SRAM Design: Device, Circuit, and Architecture

Tony T. Kim, Bo Wang, Anh Tuan Do and IEEE

2012 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC), pp.367-370

International SoC Design Conference

01/01/2012

DOI: https://doi.org/10.1109/ISOCC.2012.6407117

Abstract

Engineering

Engineering, Electrical & Electronic

Science & Technology

Technology

High energy efficient ultra-low voltage SRAMs play a key role in many emerging ultra-low power applications. However, design of SRAMs for reliable ultra-low voltage operation is challenging due to various problems. In this paper, we explore various ultra-low voltage SRAM design techniques for improving energy efficiency. Effect of MTCMOS on energy efficiency improvement, circuit techniques for ultra-low voltage operation, and architectural considerations will be presented.

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Title: High Energy Efficient Ultra-low Voltage SRAM Design: Device, Circuit, and Architecture
Creators - without role: Tony T. Kim - Nanyang Technological University
Bo Wang - Nanyang Technological University
Anh Tuan Do - Supreme Council Of Health
IEEE
Publication Details: 2012 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC), pp.367-370
Series: International SoC Design Conference
Publisher: IEEE
Number of pages: 4
Grant note: RG 23/10 ( M52040142) / Academic Research Fund (AcRF) Tier1, Singapore
Identifiers: 9912746409846
Academic Unit: ISTD Pillar
Language: English
Resource Type: Conference proceeding

High Energy Efficient Ultra-low Voltage SRAM Design: Device, Circuit, and Architecture

Abstract

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