Abstract
Higher-V-th devices in the cross-coupled latches and the write access transistors, and lower-V-th devices in the read ports are preferred for reducing leakage current without sacrificing performance. However, at ultra-low supply voltage levels, higher-V-th devices can retard or nullify energy efficiency due to substantially slower write speed than read. This paper presents energy efficiency maximization techniques for 8T SRAMs utilizing multi-threshold CMOS (MTCMOS) technology and various design techniques. Simulation results using a commercial 65 nm technology show that the SRAM energy efficiency can improved up to 33x through MTCMOS and prior power reduction and performance boosting techniques.