Abstract
The reliability and failure analysis of high-κ devices plays an important role in CMOS compatible logic and memory devices. Softer stages of dielectric degradation and breakdown deserve in-depth studies given their relevance and finite probability of occurrence in the 14 nm and sub-10 nm CMOS technology nodes of the future. This study presents a multi-physics based percolation framework model to simulate the dynamics of the sequential and competitive evolution of soft breakdown (SBD) spots during degradation of a dual-layer high-κ/interfacial layer (HK-IL) dielectric stack. The presented model leverages on the combined use of Kinetic Monte Carlo (KMC) routine to describe the microstructural variations and stochastics of defect nucleation and growth as well as the finite element model (FEM) to quantify the spatio-temporal evolution of the potential, field and temperature distributions in the stack. Furthermore, the model reveals a statistic distribution for SBD and a preferential correlation of the breakdown sites to the grain boundary spots.