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Network-on-Chip-Centric Accelerator Architectures for Edge AI Computing
Conference proceeding

Network-on-Chip-Centric Accelerator Architectures for Edge AI Computing

Bo Wang, Ke Dong, Nurul Akhira Binte Zakaria, Mohit Upadhyay, Weng-Fai Wong, Li-Shiuan Peh and IEEE
2022 19th International SoC Design Conference (ISOCC), pp.243-244
19/10/2022
DOI: https://doi.org/10.1109/ISOCC56007.2022.10031356

Abstract

accelerator Accelerator architectures Artificial intelligence edge computing Energy efficiency Memory management Network-on-Chip Neural networks Task analysis Training
In this paper, we present a Network-on-Chip-centric (NoC-centric) design technique for edge AI accelerator architectures. The technique enables NoC with compute capability, eliminates the need of using extra cores or frequent access to memory for neural network computing and eventually improves accuracy and energy efficiency. We demonstrate the dedicated, software-configurable NoCs with on-device inference and training tasks and show the architectures can achieve 2.8x and 2.1x lower energy per classification compared to state-of-the-art baselines, respectively.

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