Abstract
Physical mechanisms governing dielectric breakdown in planar devices have been well studied in the past [1, 2]. However, their extension to the study of non-planar FinFET structures has not received much attention, partly due to the assumption that the kinetics of failure would remain the same. We reveal in this study that this assumption is not true using advanced physical characterization techniques (TEM/EDX/EELS) as well as electrical-statistical tests and multiphysics simulations. The key findings of the study may be summarized as follows : (1) Progressive and hard breakdown in FinFETs is governed by silicon epitaxial defects originating from the channel; The location of breakdown is almost always at the bottom corners of the fin; (3) Area scaling is invalid for fin width and height, but valid only for fin length and count; (4) Bimodal distributions are observed in TDDB due to dielectric microstructure variations; (5) Zero-bias drain breakdown events are localized in the central fins due to self-heating intensification and shift significantly towards the source when small drain bias is applied and (6) Clustering model is necessary to explain the stochastics of TDDB in FinFETs due to geometry induced non-uniform spatial electric field patterns.