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PCMOS-based hardware implementation of Bayesian network
Conference proceeding

PCMOS-based hardware implementation of Bayesian network

Zhang Weijia, Goh Wang Ling, Kiat Seng Yeo and IEEE
2007 IEEE Conference on Electron Devices and Solid-State Circuits, pp.337-340
IEEE International Conference on Electron Devices and Solid-State Circuits
01/01/2007
DOI: https://doi.org/10.1109/EDSSC.2007.4450131

Abstract

Engineering Engineering, Electrical & Electronic Science & Technology Technology
Bayesian network [1] has received considerable attention in a great variety of research areas such as for artificial intelligence, bioinformatics, medicine, engineering, image processing, and various kinds of decision support systems. But up till now, most of the investigation on Bayesian network has been on its theory, algorithms and software implementations. This paper presents the Bayesian network from a totally new perspective--hardware circuit implementation. By using the new-born technology of Probabilistic CMOS (PCMOS) [2]-[5] and taking advantage of the statistical properties of simple logic gates, the Bayesian network can be constructed using hardware circuits. Such hardware implementation revealed the advantages in aspects of power consumption, delay time and quality of randomness.

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