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Stress-induced voiding beneath vias with wide copper metal leads
Conference proceeding

Stress-induced voiding beneath vias with wide copper metal leads

Y.K. Lim, Y.H. Lim, N.R. Kamat, A. See, T.J. Lee and K.L. Pey
Proceedings of the 11th International Symposium on the Physical & Failure Analysis of Integrated Circuits : IPFA 2004 : [July 5-8, 2004, Taiwan, (CONF 11), pp.103-106
2004
DOI: https://doi.org/10.1109/IPFA.2004.1345556

Abstract

Annealing Artificial intelligence Atherosclerosis Copper Dielectrics Lead Robustness Samarium Stress Very large scale integration
The phenomenon of stress-induced voiding beneath vias with wide copper (Cu) metal leads was studied using via chain structures stressed at temperatures ranging from 150/spl deg/C to 200/spl deg/C. After a 1000-hour stress migration (SM) test, via chain structures with extremely high resistance were mainly observed at the edge of the wafer. In addition, it was found that the geometrical dependency of stress-induced voiding could possibly be eliminated with increased process robustness. Dual-via interconnects were also proven to improve SM performance and for the first time, advanced physical analysis techniques were employed to study the cause of the improvement.

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