Abstract
It has been recently shown that the progressive breakdown (BD) is the dominant BD mode under operating conditions in CMOS circuits. Progressive BD at operating voltages can be very slow,with respect to the conditions of standard accelerated tests. It may take many years to reach gate leak-age levels large enough to appreciably disturb the circuit operation. The disturb level depends on the post-BD gate oxide conductance. For example, in an SRAM cell, to lose the noise margin for correct operation, BD spot resistances below about 50 k/spl Omega/ have to be reached. To correctly predict the behavior of a circuit with one or more transistors in BD, it is important to have an accurate model of the conduction through the BD spot during progressive BD. For a correct modeling it is, in turn, necessary to determine the physical structure of the BD spot. We have focused our study on trying to determine this structure during progressive BD. Based on this analysis we propose a quantitative model of post-BD conductance. hi this paper we present the main results of this activity.