Abstract
Stress migration (SM) and electromigration (EM) are key reliability concerns for advanced metallization in nanoscale CMOS technologies. In this paper, the interaction between these two mechanisms is studied in dual-damascene Cu/low-k interconnects. It is found that these mechanisms are not independent; EM failure time could be strongly affected by the presence of residual stress induced by SM, causing significant EM lifetime degradation. The reliability implication of the residual stress in copper interconnects on the EM is further investigated at the voiding site using transmission electron microscopy (TEM) failure analysis. A failure mechanism model is proposed to explain the lifetime degradation due to vacancy accumulation near the voiding via. The vacancy accumulation leads to higher tensile stress and shortens the time to reach the critical stress (sigma(crit)) for void nucleation.