Abstract
Driven by the ever-increasing demand of computation capability and information storage, the microelectronic technology nodes have inevitably been pushed towards smaller dimensions, higher performance and more reliable operation schemes. How-ever, the dilemma between high performance and reliable operation is always an ob-stacle in the development of next generation technology. The degradation of advanced logic and memory devices may rely on multiple intrinsic and extrinsic failure factors which make the failure analysis and reliability assessment challenging especially in sub-14 nm technology nodes. The traditional assumptions of reliability theory includ-ing Poisson process, area scaling and weakest link may not be applied in 3D structure and nanoscale dimensions. The reliability models that were so successfully applied in the past to planner structures may not be sufficient to describe the stochastic nature of the degradation behavior for present-day and future 3D devices. The reliability mod-elling and prediction has to be robust enough and parameter-sensitive to be applied in the design verification with diverse layouts and parameters. In this thesis, we first introduce the research background and literature review of the main topics in this front end of line reliability research domain. The physical, electrical, statistical analysis methods and stochastic modelling approach are briefly demonstrated. The key findings of this thesis can be listed as follows: • Metal-insulator-metal Resistive Random Access Memory — We demonstrate the switching mechanism, physical information of the filamentation process and com-positional evolution during SET and RESET stages. The shape of filaments and the dynamic evolution of switching phenomenon is well studied. The corre-sponding simulation study reveals that the formation of substrate defects is due to low activation energy at preferred growth direction. • Metal-insulator-metal Resistive Random Access Memory — Enabled by the 3D tomography technique and compositional analysis, we confirm that the defects prefer to cluster at the edge of crossbar structures due to low quality peripheral materials and process induced traps. • Split Gate Non-volatile Memory — The stochastic modelling approach gives a good correlation with the experimental data. The prediction of retention test proves that current design parameters are safe for the reliability requirements. The oxide layer between erase gate and floating gate is proved to be the weakest link for degradation, caused by the intensive electrical field enhancement during the erase process. • High-?/Interfacial Layer Logic Stack — The dynamics of the sequential and com-petitive evolution of soft breakdown spots during degradation process is well simulated by the proposed Kinetic Monte Carlo + Finite Element Method ap-proach. The impact of process induced traps and process variation on degrada-tion mechanism is carefully assessed. • FinFET Devices — Combining Metropolis Monte Carlo + Finite Element Method stochastic simulations approach and reliability test data with in-depth physical analysis insights, a complete post-mortem study on FinFET dielectric breakdown is presented. The dielectric breakdown induced epitaxy is confirmed to be the dominant mechanism governing the degradation process. The bimodal cluster-ing model provides the best representation of FinFET failure time data and the bimodality originates from the non-uniform field distribution and from local vari-ations in the microstructure. • Novel Devices — The robust modelling approach is applied to the reliability pre-diction of multiple tasks including Gate-all-around devices, Nano-crystal based memory and FinFET reliability prediction under extreme working conditions. The proposed stochastic simulation approach can be applied as a design for reli-ability tool to predict the reliability metrics of diverse device structures.