Abstract
In today’s deep learning era, advancement in artificial intelligence (AI) model is achieved with bigger training datasets that have transformed the industries by providing more significant and precise insights. However, bigger is not always better. The problem with training high-performance AI models and deploying such models entails a tremendous amount of computational power. Cloud-based video analytics (AI) has proven to be powerful in entrenching features for greater scalability on computational power, data redundancy, quick deployment, and regulatory compliance. However, it fails to perform for applications with low internet bandwidth, mission-critical on-the-fly decision making thereby resulting in a substantial amount of the by product - carbon emission from the cooling systems to keep the datacenters operational within a temperature range of 21°C ~ 24°C. Edge computing is a new approach to network architecture, where the data processing function is relocated closer to where the data is collected and analysed in real-time. Every snapshot of data does not get transmitted over to a central server for processing, by which the network latency is drastically reduced with enhanced performance for real- time applications such as convolution neural network (CNN) based image classification applications. Placing the memory and computational logic on a single chip further reduces the computational power of edge systems, by avoiding the von-Neumann memory wall created during a memory read and write operation. This performance improvement fosters the development of in-memory computation architecture and revitalizes data center’s increasingly unacceptable levels of power utilization. Resistive Random Access Memory (RRAM), notably popular among emerging memory technologies, serves very useful for fabricating low-power parallel processing in-memory computational systems with integrated synaptic memory for CNN applications. Despite all of its benefits, the real- world metal-oxide RRAM applications are notably restrained due to the cycle-to-cycle and device-to-device variability inherent in the device switching mechanism. We propose a Look-Up-Table model to extrapolate the electrical resistance variability of RRAM device array fabricated in the university cleanroom setup and encode it into fully trained commercial CNN (AlexNet, GoogleNet and MobileNet) trained weights for quantifying the impact of RRAM variability on the CNN prediction accuracy in a digital regime by encoding the logic bits 1’s and 0’s as high resistive state (HRS) and low resistive state (LRS), respectively, of the given RRAM. We have further applied RRAM synaptic memory simulation framework on two extreme possible architectures, namely the fully serial (FSS) and fully parallel (FPS) systems of today’s CNN algorithms, to record the CNN prediction accuracy trend as a function of RRAM variability. Significant studies have shown the application of RRAM as a basic digital logic; there is yet an avenue to explore the use of RRAM as universal logic gates Abstract (NAND and NOR) to construct a 32-bit floating point (FP32) operator. Thus, the modern CNN with deep hidden layers benefits from power- efficient matrix convolution and gradient descent optimization logic using the RRAM-based FP32 computational logic. Hence, an edge learning framework is demonstrated using digital RRAM-NAND/NOR universal gates. The RRAM universal gates are further used to design the convolution operation (forward pass) and gradient descent optimization algorithm (backward pass), which are applied for building lower-power CNN applications. The human brain is inspired by its ultra-low power operations with slow and massively parallel processing to solve complex problems. We have implemented a low-speed parallel processing CNN training system that mimics the human brain and studies the training performance using RRAM digital computational logic. We have proposed a novel probabilistic approach to control the RRAM variability, which takes up less silicon real estate compared to the conventional techniques of reprogramming and verification methods. A simple RRAM array, designed as cache memory and used for the reprogramming scheme without verification to keep the RRAM validation process quick and straightforward, known as Maximum Count Binary Comparator (MCBC) is proposed. A novel methodology is demonstrated for edge learning framework (forward pass and backward pass) using digital RRAMNAND/ NOR universal gates integrated with MCBC to control the impact of RRAM variability and to quantify the RRAM variability on the CNN inferencing and training prediction accuracy for wide current compliances ranging from 2 to 250µA for ultra-low power IoT applications. We have also demonstrated a practical implementation of the RRAM-NAND-based standard cell (using 65nm CMOS technology) and simulated it using the SPICE model. The RRAM crossbar array configured as a vector-matrix multiplication and accumulation proves helpful for performing a power-optimized convolution operation on the forward pass of the CNN architecture. However, the extra peripheral circuits such as ADC and DAC used for interfacing the mixed signal domain certainly adds on to a load of additional resources, which needs to be considered for future research in circuit design and optimization. In summary, our LUT-based digital methodology and simulation framework does enable fabricating digital RRAM computational logic as an inmemory system for edge IoT CNN applications with acceptable accuracies ranging from 40-80% for 400-1000X reduction in power consumption.