Abstract
Presently, the demand for data transmission capability is dramatically increasing due to the new bandwidth-intensive services such as the internet of things, cloud-computing, and even vehicle-to-vehicle communication for self-driving vehicles. Another trend is that the electromagnetic frequency for transmission is changing. Currently, the dominant wireless transmission frequency for near-field communication is Wi-Fi at 2.4/5 GHz. However, visible light communication (VLC) would be efficient enough not only for long distance communication through fiber optic cables, but also for short distances with the signal transmitted through high frequency flickering and modulation of the light intensity through the air. Synchronous Optical Networking (SONET) standard is used for data transmission via fiber optic networks. SONET OC-96 is the standard for 5 Gb/s data transmission. In addition, advances in CMOS integration with laser diodes and photodiodes onto the same chip as well as its ability to be mass produced at low cost allow the viability for VLC transmitters and receivers to be placed in every single smart device for it to be widely available. In a VLC system, the transimpedance amplifier (TIA) is found in the receiver module as the first chip block after the photodiode. As the first circuit block in the optical receiver front-end connecting the photodiode to subsequent amplifiers, the TIA is critical in determining the bandwidth, noise and sensitivity of the receiver and thus the entire VLC system. The photodiode is required to be large to capture enough light energy signal for a perceptible current. Thus, the main TIA design challenge is to compensate the large parasitic capacitive load of the photodiode that contributes to the dominant pole and lowers the bandwidth. This can be done by lowering the input impedance to compensate for the large capacitive load. Apart from a large bandwidth, other desirable key parameters for TIA designs include a large gain, large dynamic range, low noise, low power consumption and small area. These parameters are often trade-offs of each other, with gain-bandwidth being the most prominent, characterized by a transimpedance curve. Thus, most TIA amplifiers would try to push this transimpedance curve outward through their circuit designs. The main objective of the current work in this thesis is to design a 4 GHz variable-gain TIA for the VLC system that can achieve 5 Gb/s data transmission and a transimpedance gain of above 55 dBO. Previous TIA designs done by this author are presented ending with the final proposed design to show the design progression. The specific design requirements, design 4 challenges and various techniques used to achieve desirable parameters such as bandwidth-enhancement and low-noise are also presented. In the proposed design, a unique inductorless Single-to-Differential Cross-coupled Variable-gain Transimpedance Amplifier (SDCV-TIA) using UMC CMOS 40 nm process is presented. By being inductorless yet having a large bandwidth of 4 GHz, the proposed SDCV-TIA saves chip area and hence lower the cost. The proposed SDCV-TIA consists of a single-to-differential input stage with unique dual cross-coupling feedbacks and feedforwards, while the stage after it is a ???? doubler common-source intermediate stage with a unique combined active inductor and capacitive degeneration for bandwidth-maintenance as well as a common-mode feedback for linearization of the differential signal. Both the input and intermediate stages have gain-varying and peaking-varying functions controlled by biasing voltages. There are many unique features and advantages in the proposed cross-coupled feedback Single-to-Differential (S2D) input stage design. Firstly, the cross-coupling feedbacks in the input stage both reduces the input impedance and increases the gain by reusing the core transistors as both common-gates (CG) and common-sources (CS). Secondly, because the design preserves the regulated cascode (RGC) stage while having a differential output, the frequency response can be manipulated by adding a RC low pass filter within the input stage. The dominant pole as well as the zero generated by the RC filter can be shifted by varying the resistance at input, allowing the zero to adjust together with a change in gain, keeping the frequency response flat throughout gain-variation and achieving a stable design. Thirdly, the unique single-to-differential input to output design enables a differential signal output into the subsequent intermediate stage. The dual feedback in the cross-coupling design helps to generate the AC differential output, while the same component sizes on both sides and current source help equalize the DC voltages across the differential output. Hence, the proposed design is unique as it can do the single-to-differential conversion in a single stage without any need for a dummy circuit. It also does not need an additional large low-pass filter capacitor as in a traditional single-to-differential converter. There are also many unique features and advantages in the proposed intermediate stage design. It is an active inductor with capacitive degeneration ???? Doubler (fTD) intermediate stage. Firstly, the unique active inductor combined with capacitive degeneration design allows both gain and peaking variation since it also controls a very prominent zero which control peaking in the frequency response. Secondly, the ???? doubler design helps to maintain the bandwidth while increasing the linearity of the differential signal as well as help better 5 matching to the output buffer. Thirdly, the common-mode feedback circuit (CMFB) within the intermediate stage further equalizes the DC voltage as well as cancelling the AC common-mode noise across the differential sides. Hence, this further ensures the linearity and complete opposition of the differential signal. The buffer stage consists of a simple differential CS and common-drain (CD) that is approximately gain-neutral. The design has been sent to the foundry and taped-out with its measurement results consistent with the post-layout simulation results. The results have been sent to a journal [13] and are also presented in this thesis. The SDCV-TIA has a measured gain range of 37.5 – 58.7 dBO with bandwidth at or above 4 GHz throughout the gain range, which is achieved by varying the gains in both the S2D input and fTD intermediate stages. The frequency response is also flat throughout due to the varying-peaking design of both stages. The reported results are from testing with a photodiode capacitive load of 0.5 pF. The wide gain range converts into an input current dynamic range of 33.2 µA – 1.46 mA which covers the photodiode current output. The SDCV-TIA has an input referred noise current of 10.7 pA/v????, a sensitivity of -49.8 dBm, a core DC power consumption of 7.84 mW and a compact core area of 39 µm × 26 µm. The proposed design has been compared to other recent journal papers using gain, bandwidth, gain range, photodiode capacitive load and power consumption as criteria in a figure of merit (FOM). It has the highest FOM compared to the other recent variable gain TIA designs, proving that the SDCV-TIA is the best TIA design. In summary, the current work in this thesis focuses on the TIA designs using CMOS transistors for mature technologies such as 180 nm as well as newer technologies such as 40 nm which is the most critical chip block in the front-end of the VLC system. The design challenges, novelty, simulation and measurement results of the proposed SDCV-TIA design have been addressed and it exceeds in performance when compared to other recently published variable-gain TIA designs.