Abstract
Due to the outburst growth of the hand-held smart devices that need the internet connection, the low frequency spectrum resource has reached to its limit, making it impossible to allocate any frequency band to the newly emerged applications. Therefore the 60-GHz band offers an alternative solution at the high frequency band with an increased bandwidth to achieve the Giga-bits-per-second (Gbps) data rate. Owning to the achievement of advanced integrated circuit (IC) progress, the 60-GHz wireless communication system is able to be implemented on chip with reduced area. In 60-GHz wireless communication systems, transceivers are responsible for transferring data among different wireless terminals at certain carrier frequencies. In transceivers, phase-locked loops (PLLs) used to synthesize the local frequency play a significant role in signal frequency conversion between the radio frequency (RF) band and the baseband. As a key block in PLLs, voltage-controlled oscillator (VCO) is therefore required to be designed at high operation frequency with wide frequency tuning range (FTR) and low phase noise. However, at high operating frequencies especially in millimeter-wave (mm-Wave) range, VCO designs with low power consumption, wide FTR and low phase noise still remains as a challenging task. On the other hand, the silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) technology has gained popularity in many mm-Wave circuits design, such as power amplifiers (PAs) and low-noise amplifiers (LNAs). Thus, integrating a VCO with these building blocks on a single chip would be desirable from a system design prospective. Consequently, the bipolar complementary metal-oxide-semiconductor (BiCMOS) process lends itself as a more and more favorable choice. In order to increase the VCO FTR, two methods are usually adopted. The first one is to increase the tunable range of the associated tank inductors and capacitors across the full controlled voltage, while the other one is to reduce the parasitic capacitance contributed II by the transistor. However, considering the trade-offs among FTR, phase noise and dc power consumption, improving these parameters simultaneously is not easy. In this thesis, improved VCOs are designed for 60-GHz applications based on the two methods discussed above. In the first design, a compact VCO with two switching cores by using a triple-coil coupling transformer (TCCT) is demonstrated. The TCCT is employed to connect two VCO cores with different operation frequencies, which are overlapped with each other, thus an extended continuous frequency band can be formed. In addition, the differential voltage output nodes could remain unchanged across different switching cores. The proposed VCO achieves overall FTR of 15.2%, from 28.62 GHz to 33.32 GHz and the overall LC-tank size could be reduced to 0.012 mm2, which is highly preferred by mm-Wave applications. Besides, the stability issue is eliminated since the proposed VCO always operate in the stable mode at the presence of multiple resonance frequencies. What is more, during the operation, the two switching cores would benefit from each other in the view of start-up condition as well as phase noise reduction. The measured phase noise varies from -98.0 dBc/Hz to -102.7 dBc/Hz at 1 MHz offset frequency. Furthermore, the operation frequency and FTR have conventionally been deteriorated by the transistor parasitic capacitance associated with the layout, especially at mm-Wave region. The HBT base resistor also needs careful consideration when a low power VCO is required. However, these parasitics are difficult to be eliminated as they are inherently determined by the fabrication process. In the second design, a transformer-based dc-decoupled VCO is presented, in which not only parasitic capacitance of active devices can be reduced, but also phase noise can be improved with minimized power consumption. The oscillation frequency of the VCO can be tuned from 28.45 GHz to 33.08 GHz, which indicates a FTR of 15.1%. In addition, the proposed VCO achieves a best phase noise of -102.8 dBc/Hz at 1 MHz offset with a dc power consumption of only 6.5 mW.