Abstract
With the rapid growth of semiconductors in the consumer, industrial, and automotive sectors, the demand for embedded non-volatile memory (NVM) has also increased. Competition in compact product design is driving the embedded Flash memory technology to its scaling limit. An emerging technology named split-gate NVM has unique advantages in providing over-erase immunity and low-power high-speed operation using highly efficient source-side injection program, poly-Si-to-poly-Si Fowler–Nordheim tunnelling erase and low-voltage read. It also has a simple design and architecture, good manufacturability, high reliability, and a proven track record of meeting the specifications of both industrial and automotive applications. In this thesis, the author successfully demonstrates a functional and reliable self-aligned split-gate NVM cell, down to a very small and competitive cell size. This NVM cell is embedded into a 40 nm low power (LP) logic process with copper low-? interconnects. The self-alignment sequence with gate spacer and poly-Si chemical mechanical polishing provides a small and optimized cell that can be easily integrated into standard logic process in a modular way. This is the first time that a functional split-gate embedded Flash memory cell at 1.1 V supply voltage is demonstrated in industry using the 40 nm LP process. To meet the high requirements of automotive products, zero failure rate under harsh temperature conditions, code storage with 10 ns fast random access, endurance of at least 103 cycles and >10 years of retention, and data storage with endurance of 2 × 105 cycles and 10-year retention are required. This thesis successfully demonstrates a logic-compatible, highly reliable, automotive-grade 16 Mb split-gate NVM design test chip with the following key features: dual power supply with operating temperature from -40 to 150 ºC, maximum random read access time of 10 ns, and low active and standby power. Moving further, a product-like split-gate NVM macro (product-like chip) with a high density of 20 Mb is successfully emonstrated with high reliability performance of over 2 × 105 cycles, a sufficiently wide read margin and very high post-cycling data retention up to 150 ºC. The split-gate NVM macro has a dual power supply with input voltage fluctuations, a wide operating temperature range from -40 ºC to 150 ºC, fast byte/word program under 10 µs, and sector/chip erase under 10 ms. The macro’s random read access time is only 8 ns under the worst condition of 150 ºC. Due to the excellent performance, the developed split-gate NVM is suitable for high-speed automotive Microcontroller Unit (MCU), as well as Internet of Things, smart card, and industrial MCU applications. Kinetic Monte Carlo (KMC) and Finite-Element-Method (FEM) models are applied in simulation to study the distributions of electric field and read current under split-gate NVM erase, program, and read operations. The results of simulations match well with the device data demonstrated at a 40 nm technology. Furthermore, the degradation behaviour of the endurance of the split-gate NVM was studied by the combined KMC+FEM simulation model. The simulation results show that NVM cell erase/read current will degrade with increasing cycling, and the associated stress cell current under cycling test matches well with the experimental results. The simulation model further predicts a total endurance lifetime of about 1.5 million cycles for the developed NVM cell before reaching the leakage current specification. Such prolonged cycling test cannot be easily determined by standard reliability test due to a prolonged time needed. The simulated electric field distribution successfully reveals the reliability weak points of the split-gate NVM cell as well as identifying that the highest electric field is associated with the erase-gate (EG). This provides us valuable information to identify the reliability weak points of the NVM cells, which are especially essential for overcoming the scaling challenge of NVM cell. This is the first report in the literature of such split-gate NVM intrinsic reliability study. Based on the reliability weak points identified by the simulation mentioned above, the author successfully determines the physical failures of the EG oxide under both soft breakdown (SBD) and hard breakdown (HBD) using a unique nanoprobe stressing method. The novel nanoprobing technique developed allows us to selectively stress only a few NVM bits or a localized area of interest, which is typically smaller than 6 µm in length (comparable to the maximum length of a focused ion beam (FIB) sample). As a result, the breakdown path of interest can be analyzed by transmission electron microscopy (TEM) with high probability. The TEM results clearly show that the percolation (or breakdown) path, which has a size of about 100 nm, has caused an electrical short between its Ni-silicided electrode and Si substrate. This is the first report on using TEM to study the physical defects responsible for EG oxide breakdown in split-gate NVM under erase condition. The effect of the extra NVM thermal budget on static random-access memory (SRAM) performance in embedded Integrated Circuit (IC) logic process was investigated. Due to a severe threshold voltage shift in SRAM in the presence of the extra NVM thermal budget, an extra step of carbon implant into polycrystalline silicon is proposed. Carbon implant was found to impede polycrystalline silicon grain growth, leading to an elimination of poly-depletion effect. Thus, carbon implant provides a useful and simple solution for future embedded NVM ICs beyond the 40 nm technology node.