Abstract
Technological node advancement in semiconductors is a highly anticipated process as it provides significant increase in processing power in both central processing units (CPUs) and graphic processing units (GPU). Furthermore, cost savings are also an integral part of technological node advancement as the units are scaled smaller; the unit area size would also drop. Therefore, more units can be produced per wafer during technological node advancement. However, with the recent improvement to 7nm units, cost savings are drastically reduced due to the exponential increase in cost for research and development. Automating the failure analysis process would bring about massive cost savings in research and development for future technological nodes. With the recent advancement in computer vision and artificial intelligence, convolutional neural networks have been proven to be close to the state of the art in classifying images. This thesis aims to capitalize on the advancements in convolutional neural networks to aid the failure analysis process through comparison and classification of defects in a microscopy image of a microchip. In the thesis, we discuss why traditional image comparison techniques are harder to be applied for this problem. Turning to residual convolutional neural networks, we were able to obtain a classification accuracy of 83% despite the lack of a large sample size. To further increase the classification accuracy of the model and to overcome the lack of a large defective image dataset, a Siamese network was utilized. The Siamese network aims to leverage on the larger amount of good data’s sample size that we have. Furthermore, feature engineering was done iii to improve and fine tune the Siamese network for the classification of defects in the microscopy images of the microchip.