Abstract
In recent years, the field of integrated circuit (IC) design has undergone a paradigm shift, marked by the increase in democratisation of design processes. This movement is accelerated by the recent, yet rapid development of large language models (LLM) and generative AI, and the maturation of open-source design tool chains.
The thesis presents a new approach to hardware design implementation, driven by the recent developments in technology, combining the advances of natural language processing (NLP) and Application Specific Integrated Circuit (ASIC) design. This work can be divided into two parts: the usage of open-source IC design tools and leveraging the capabilities of open-source LLM to generate HDL.
First, the study demonstrates the use of open-source hardware design tools, with analysis and comparison of OpenLane, an open-source design tool chain, against its existing commercial counterpart. This study addresses and showcases the capabilities, advantages, and limitations of using open-source tools in ASIC design.
Next, the focus of the research shifts into the usage of generative AI and open-source design tools together, demonstrating the possibility of bringing AI-generated designs to a manufacturable ASIC.
Lastly, the fine-tuning of generative AI models to generate hardware descriptive language, specifically Verilog HDL code. The effectiveness and accuracy of the generated Verilog code are then evaluated using VerilogEval, an LLM benchmarking tool developed by a team from NVIDIA.