Abstract
In recent years, Artificial Intelligence (AI) and its related technologies was expanding by leaps and bounds, including Machine Learning (ML), Deep Learning (DL) and Neural Network (NN). Convolutional Neural Network (CNN) is the most important technology in the field of Image Recognition. CNN algorithms usually must process extremely large amounts of data, which results in heavy computations and complex operation procedures. Traditional calculation methods require many resources, Cloud server is usually used for the computing. Due to the limitation of data transmission speed, the clients cannot obtain the real-time result of inference. It is a common practice to execute AI algorithms on mobile devices to avoid latency, transmission energy consumption and privacy problems. For this reason, a specified hardware architecture with high-performance should be designed to perform the CNN models. This work proposed a high-performance chip for CNN inference. Algorithmic Noise-Tolerance (ANT) architecture is used as the core technology for modification due to the error tolerance characteristics of CNN. Dividing the overall hardware architecture into main and secondary block and select the appropriate operation mode according to the importance of image features. Through the method proposed in this thesis, split the original calculations, and remove the redundant parts. This proposed chip was simulated on VGG16 model using the CIFAR-10 dataset. Experiment results show that the proposed CNN chip achieved about 90% power reduction, 45% area reduction, and more than 20% reduction in computing time with 1.25% drop of inference accuracy.