Abstract
The shrinking of transistors as a result of advancements in semiconductor fabrication technology have resulted in higher performance and lower computing costs for microprocessors. New and existing failure mechanisms have to be understood and suitable corrective measures must be implemented to drive the advancements in fabrication technology. Electrical Fault Isolation (EFI) is a preliminary step in failure analysis, EFI is a methodological approach to identification of root cause defects within a device. Advancement in technology from planar transistors to FinFETs has substantially increased the heat confinement in transistors, The self-heating (SH) effects in FinFETs are a major cause of concern for device operation and reliability. Shrinking transistor nodes requires EFI setups with better spatial resolution to accurately perform fault isolation. To achieve better spatial resolution, shorter wavelength lasers are proposed. Since shorter wavelength lasers are absorbed more by bulk silicon, we are constrained to remove the bulk silicon which further aggravates the heat confinement. In this work, we investigate the heat generation and dissipation in a modern microprocessor from a fault isolation perspective. ANSYS® Finite Element Modelling (FEM) toolkit was used to simulate and characterize monolithic and 3D stacked devices when subjected to fault isolation conditions. The effectiveness of the existing cooling solutions was identified using simulations. Our key contribution here is the development of a comprehensive thermal simulation flow to determine the power envelope which helps in avoiding thermal runway during fault isolation.