Abstract
3D die stacking is one of the packaging solutions to accommodate the increasing demand for ultra-short-reach (USR) interconnects, increased performance and functionality, miniaturization in size and weight, and reduced power consumption requirements [1]. However, the complexity of the 3D stacking structure brought a new challenge to failure analysis as defects need to be localized not only in the x- & y-directions but also in the z-direction. Lock-in Thermography (LIT) is one of the Electrical Fault Isolation (EFI) tools that can be used for isolating defects in x-, y-, and z- directions non-destructively. However, determining the defects that are deeply buried and situated near the die edge in stacked die devices via LIT remains challenging. As a strong artificial thermal emission site is detected outside of the die region while at the defect site itself, weak or no emitted thermal signal can be detected. In this research project, the ANSYS workbench is used as a Finite Element (FE) simulator to study the thermal spreading of a defect located at different lateral locations in x- & y-directions as well as different depths in the z-direction of flip chip and stacked die devices. The critical position where heat spreading in the horizontal direction is faster than the vertical direction is determined via simulation for the flip chip and the X3D stacked die device, respectively. The simulation results have a good match with the LIT results detected in the actual defect samples. Thermal delays for a heat source to simulate a defect placed at different depths in the flip chip and the X3D stacked die device have also been studied in this project. A good match between the thermal delays obtained from thermal simulations and the theoretically calculated thermal delay with a +/- 10% deviation.