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0.6mW 6.3 GHz 40nm CMOS divide-by-2/3 prescaler using heterodyne phase-locking technique
Journal article   Peer reviewed

0.6mW 6.3 GHz 40nm CMOS divide-by-2/3 prescaler using heterodyne phase-locking technique

X.P. Yu, Z.H. Lu, W.M. Lim and K.S. Yeo
Electronics letters, Vol.49(7), pp.471-472
28/03/2013

Abstract

Microwave technology
A dual-modulus prescaler based on the heterodyne phase-locking technique is presented. Different to the conventional LC tank based phase-locked loop, by directly locking at two injection-locked ring oscillators simultaneously, a dual-modulus operation is achieved while a wide-range operating, significantly reduced settling time and low power consumption are achieved. Implemented in a standard 40nm CMOS process, the proposed divide-by-2 and 3 dual-modulus prescaler achieves an operating frequency of 6.3GHz with a measured power consumption of 0.6mW from a 1.1V supply.
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https://doi.org/10.1049/el.2013.0584View
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