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A 19-to-45 GHz High-Efficiency Frequency Doubler Using Multi-Port Darlington Cell With Fundamental and Second-Harmonic Pole-Stagger in 55-nm CMOS
Journal article   Peer reviewed

A 19-to-45 GHz High-Efficiency Frequency Doubler Using Multi-Port Darlington Cell With Fundamental and Second-Harmonic Pole-Stagger in 55-nm CMOS

Zhen Yang, Fanyi Meng, Bing Liu, Nengxu Zhu, Zenglong Zhao and Kaixue Ma
IEEE journal of solid-state circuits, Vol.60(10), pp.3843-3858
01/10/2025

Abstract

Engineering Engineering, Electrical & Electronic Science & Technology Technology
A millimeter-wave (mm-Wave) ultra-wideband high-efficiency frequency doubler without any buffer and switching is proposed in this article. The proposed frequency doubler employs a new multi-port Darlington cell (MPDC) pair to incorporate a secondary feedback path for the 2nd harmonic generated at the drain terminal to the gate terminal. The positive feedback is created to override the negative feedback from gate-to-drain parasitics for drain efficiency enhancement. For frequency extension, the pole-stagger technique is adopted for the fundamental input and second-harmonic feedback voltage at the gate terminal. As a result, the proposed MPDC frequency doubler demonstrated a 19-45 GHz (81.25%) 3-dB instantaneous bandwidth, a 25-35 GHz (41.27%) 1-dB instantaneous bandwidth, a 23.2% peak drain efficiency (eta(D)) (>15% from 20 to 41 GHz), and a 17.7% peak total efficiency (eta(total)) (>10% from 20 to 42 GHz) in 55-nm bulk CMOS technology.

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