Abstract
This paper presents the design and verification of a proposed 30-GHz power-efficient phase-locked loop (PLL) frequency synthesizer for 60-GHz applications. Fabricated by a commercial 0.18-μm SiGe BiCMOS process, the synthesizer employs coupled LC tank voltage-controlled oscillator, high power-added efficiency amplifier, reconfigurable divider realizing fractional division ratios for choice of multiple reference frequencies and low operation power, a programmable charge pump, an internal loop filter, and an integrated slave serial peripheral interface. The PLL synthesizer (PLLS) provides output frequency from 29.5 to 33.4 GHz with phase noise of -97 dBc/Hz at 1-MHz offset. The integrated phase noise over the frequency of 10 kHz-10 MHz is 2.05° rms at a frequency of 30.24 GHz. Operating with a single 1.8-V supply voltage, the PLLS consumes a low power of 63 mW and occupies an area of 2.8 mm × 1.86 mm.