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A 93.4-104.8-GHz 57-mW Fractional- Cascaded PLL With True In-Phase Injection-Coupled QVCO in 65-nm CMOS Technology
Journal article   Peer reviewed

A 93.4-104.8-GHz 57-mW Fractional- Cascaded PLL With True In-Phase Injection-Coupled QVCO in 65-nm CMOS Technology

Xiang Yi, Zhipeng Liang, Guangyin Feng, Fanyi Meng, Cheng Wang, Chenyang Li, Kaituo Yang, Bei Liu and Chirn Chye Boon
IEEE transactions on microwave theory and techniques, Vol.67(6), pp.2370-2381
06/2019

Abstract

Bandwidth Cascaded phase-locked loop (PLL) Circuit synthesis CMOS technology CMOS voltage-controlled oscillator (VCO) frequency synthesizer in-phase injection-coupled (IPIC) integrated circuit (IC) Integrated circuits low phase noise millimeter wave (mm-wave) Phase locked loops Phase noise quadrature VCO (QVCO) subsampling PLL (SSPLL) Voltage-controlled oscillators W-band
A fully integrated 93.4-104.8-GHz 57-mW fractional- {N} cascaded phase-locked loop (PLL) with true in-phase injection-coupled quadrature voltage-controlled oscillator (QVCO) is reported. By cascading the fractional- {N} PLL and the subsampling PLL, good phase noise, high resolution, and wide acquisition range are achieved simultaneously. The transformer-based true in-phase injection coupled technique is adopted in the QVCO to obtain both low phase noise and low-power consumption. The proposed cascaded PLL was fabricated in a 65-nm CMOS technology with silicon size of 0.88 mm 2 . The measured phase noise of QVCO and PLL is −113.26 and −106.63 dBc/Hz at 10-MHz offset, respectively. The FOM and FOM T of the QVCO at 10-MHz offset are −178.4 and −180.0 dBc/Hz, respectively. The frequency resolution of the 100-GHz output is less than 3.6 kHz.

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