Abstract
This paper presents a low-power CMOS receiving signal strength indicator (RSSI). The main architecture of the circuit adopts a six-stage limiting amplifier (LA) in a logarithmic-linear form, which shows a good performance in weak signal detection. The RSSI achieves high tolerance to process, voltage, and temperature (PVT) variations by utilizing the unique nature of branch currents in a transconductance amplifier. The power consumption is decreased by using the weak-inversion LAs. Full-waveform current rectification and summation are employed in the RSSI circuit to achieve high precision while maintaining low power consumption. Measured results show that in the 1 kHz-50MHz frequency range, the input dynamic range is wider than 70 dB within +/- 2 dB linearity error. The chip occupies an area of 0.7 mm(2) x 0.3mm(2) using a 0.18-mu m CMOS. It draws 1.3mA from a 1.8V supply.