Abstract
This article presents a fully integrated high-power and high-efficiency D -band power amplifier (PA) with two-way differential power combining in a 28-nm bulk CMOS process. The overall performance improvement is achieved mainly from three aspects. First, the effect of resistance brought by the actual matching network on performance above 100 GHz is considered in transistor selection, and the deoverstabilization technique is proposed to select structures with high output power and high efficiency at stabilization. Meanwhile, the compensating inductors are introduced in the distributed active transformer (DAT) network to reduce RF signal leakage and insertion loss of the power combiner. Finally, considering the low intrinsic transistor gain above 100 GHz in CMOS, the effect of different interstage matching network losses on the overall efficiency is analyzed to guide the optimization objectives of different matching networks, taking into account both gain and chip area. The three-stage four-way power combining PA achieves a peak gain of 19.2 dB, a measured maximum saturated output power of 15.4 dBm, a peak power-added efficiency (PAE) of 14.25%, and a high power density of 381 mW/mm(2). To the best of our knowledge, the proposed PA achieves the highest PAE in bulk CMOS-based D-band PAs with an output power greater than 15 dBm.