Abstract
This proposed work introduces a DC-DC converter with Switched-Capacitor Delay Deadtime Controller (SCD-DTC), Digitally Controlled Start-Up Block (DC-SUB), and Enhanced Unbalanced-Input Pair Zero-Current Detector (EUIP-ZCD) that helps to improve the overall power efficiency. It also introduces the discussion of key signal waveforms and the two major optimization flowcharts. This proposed DC-DC converter can simultaneously achieve optimized deadtime (body diode conduction < 3 ns) and almost fully eliminate the phenomenon of reverse inductor current (RIC). Furthermore, it also shows that it can achieve a well-regulated output voltage of 1.8 V with <0.01% of output ripple riding on it. All the post-layout simulation results are carried out using 0.18 mu m 1P6M CMOS process using Cadence Virtuoso Spectre Circuit Simulator. The silicon chip area of our proposed work (including the output pad frame) is 1.44 mm(2). The chip fabrication was sent out in January 2024 and the return of the measurement dies is expected in March 2024. The post-layout simulation results will no doubt closely resemble the measurement results since the proposed work is mostly controlled by digital blocks.