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A DSP-based video compression test-bed
Journal article   Peer reviewed

A DSP-based video compression test-bed

A.A. Kassim, F.K. Fong, K.S. Chua and S. Rangananth
Microprocessors and microsystems, Vol.20(9), pp.541-551
01/05/1997

Abstract

H.261 standard TMS320C30 Video compression
This paper presents a DSP-based video compression system that was developed to serve as a platform for the testing and implementation of different video compression algorithms. The system consists of three main functional units; the video encoder, the video decoder and the audio codec processor. Each functional unit consists of a Texas Instruments TMS320C30 digital signal processor. A complete implementation of the H.261 video communications standard on the system is also presented.

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