A Low-Power In-Memory Multiplication and Accumulation Array With Modified Radix-4 Input and Canonical Signed Digit Weights

Journal article

Peer reviewed

Rui Xiao, Yewei Zhang, Bo Wang, Yanfeng Xu, Jicong Fan, Haibin Shen and Kejie Huang

IEEE transactions on very large scale integration (VLSI) systems, Vol.31(11), pp.1700-1712

01/11/2023

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Title: A Low-Power In-Memory Multiplication and Accumulation Array With Modified Radix-4 Input and Canonical Signed Digit Weights
Creators - without role: Rui Xiao - Zhejiang University
Yewei Zhang - Zhejiang University
Bo Wang - Singapore University of Technology and Design
Yanfeng Xu - China Electronics Technology Group Corporation
Jicong Fan - China Electronics Technology Group Corporation
Haibin Shen - Zhejiang University
Kejie Huang - Zhejiang University
Publication Details: IEEE transactions on very large scale integration (VLSI) systems, Vol.31(11), pp.1700-1712
Number of pages: 13
Identifiers: 9912658309846
Academic Unit: ISTD Pillar
Language: English
Resource Type: Journal article