Abstract
This brief presents a novel CMOS compact, low-loss digital attenuator chip for low-power, scalable phased array systems. To achieve low-loss amplitude control at high-millimeter-wave (mmW) frequencies with minimal area overhead, the proposed design employs a novel series triple coupled transformer (STCT) structure, integrated with an impedance-tunable network (ITN) to enable multibit control within a compact footprint. Fabricated using a 65-nm-bulk CMOS technology, the 5-bit attenuator chip demonstrates an insertion loss (IL) as low as 3.3 dB across the 110-130 GHz with a 0.5-dB step resolution and an amplitude control range of 15.5 dB. The measured rms amplitude and phase errors are minimized to 0.4 dB and 5.2°, respectively. The core area of the chip is only 0.06 mm 2 .