Abstract
This brief presents a 5-bit capacitive-compensated low-phase-error passive attenuator for 2-to-7 GHz (S/C-Band) communication satellites. The attenuator adopts several cascaded switchable attenuation cells, in topologies of \Pi -type, T-type, reduced-T type, bridged-T type, and capacitor-bridging \Pi -type. To compensate the phase error during state switching, the \Pi -type attenuation cell is modified to capacitor-bridging \Pi -type with phase-lead compensation effects, by introducing a compensation capacitor bridging the two resistive branches. The modified cell reduces the phase error/imbalance up to 0.92°, with negligible amplitude error induced. The 5-bit passive attenuator is designed and fabricated in a 55nm CMOS. The measured results reveal a relative attenuation range of 31 dB with a step size of 1 dB. The reference state insertion loss is 5.4 dB, while the return losses of all states are below 12.5 dB. It features a low root-mean-square (RMS) amplitude error of 0.48 dB, and the highest RMS phase error of only 0.92°. The chip occupies a core area of 0.53\times0.31 mm2 and consumes negligible power.