A charge-trapping-based technique to design low-voltage BiCMOS logic circuits

Yeo Seng; S Rofail; Kiat Seng Yeo

doi:10.1109/4.654950

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A charge-trapping-based technique to design low-voltage BiCMOS logic circuits

Journal article

Peer reviewed

A charge-trapping-based technique to design low-voltage BiCMOS logic circuits

Yeo Seng, S Rofail and Kiat Seng Yeo

IEEE journal of solid-state circuits, Vol.33(1), pp.164-168

01/01/1998

DOI: https://doi.org/10.1109/4.654950

Abstract

New BiCMOS logic circuits employing a charge trapping technique are presented. The circuits include an XOR gate and an adder. Submicrometer technologies are used in the simulation and the circuits' performances are comparatively evaluated with the CMOS and that of the recently reported circuits. The proposed circuits were fabricated using a standard 0.8-mum BiCMOS process. The experimental results obtained from the fabricated chip have verified the functionality of the proposed logic gates

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Title: A charge-trapping-based technique to design low-voltage BiCMOS logic circuits
Creators - without role: Yeo Seng
S Rofail - Nanyang Technological University
Kiat Seng Yeo - Office of Provost
Publication Details: IEEE journal of solid-state circuits, Vol.33(1), pp.164-168
Number of pages: 5
Identifiers: 9912391409846
Academic Unit: Office of Provost
Language: English
Resource Type: Journal article

A charge-trapping-based technique to design low-voltage BiCMOS logic circuits

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