Abstract
A detailed methodology to perform the transient analysis of digital BiCMOS circuits is presented. The analysis takes into account high level injection effects, the capacitances at the base, and short-channel effects for the MOS drain current. The model is general and its equations are derived for delayed input signals. The effect of the input slew rate on the gate delay is evaluated. The various correlations between the device/circuit parameters and the overall delay performance are examined. The model predictions show excellent agreement with HSPICE simulated delay.