Abstract
This paper describes a redundant-binary partial-product generator (RB PPG) that is based on a five-bit recoding technique, designed to operate in a 16 × 16-bit RB parallel multiplier. It produces only half the number of partial-products generated by a conventional modified Booth's algorithm (MBA) PPG, thus leading to significantly lower circuit complexity and better speed performance for the partial-product addition circuitry that generates the final output. Unlike other five-bit recoding PPGs suggested so far, the proposed PPG does not require any additional adders to generate the non-power-of-two multiples of the multiplicand. Circuit simulations have also shown that the proposed PPG has lower power dissipation when compared to other MBA PPGs, with only a slight disadvantage in speed. As a result, the benefits gained within the partial-product addition circuitry are not compromised.