An 8-Bit in Resistive Memory Computing Core With Regulated Passive Neuron and Bitline Weight Mapping

Journal article

Peer reviewed

Yewei Zhang, Kejie Huang, Rui Xiao, Bo Wang, Yanfeng Xu, Jicong Fan and Haibin Shen

IEEE transactions on very large scale integration (VLSI) systems, Vol.30(4), pp.379-391

01/04/2022

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Title: An 8-Bit in Resistive Memory Computing Core With Regulated Passive Neuron and Bitline Weight Mapping
Creators - without role: Yewei Zhang - Zhejiang University
Kejie Huang - Zhejiang Lab
Rui Xiao - Zhejiang University
Bo Wang - Singapore University of Technology and Design
Yanfeng Xu - China Electronics Technology Group Corporation
Jicong Fan - China Electronics Technology Group Corporation
Haibin Shen - Zhejiang Lab
Publication Details: IEEE transactions on very large scale integration (VLSI) systems, Vol.30(4), pp.379-391
Number of pages: 13
Identifiers: 9912659109846
Academic Unit: ISTD Pillar
Language: English
Resource Type: Journal article